1. Field of the Invention
The present invention relates to a device and method for controlling a data storage device, such as DRAM (dynamic random access memory) and the like.
2. Description of Related Art
DRAM is generally used as a main memory for a microprocessor or the like computer. Efforts have been made to increase the capacity of this DRAM in order to improve the performance of the entire computer systems.
In recent years, there has been increasing demand not only to increase the memory capacity, but also to increase the speed of microprocessors by increasing the data transfer rate of the DRAM, and to create more diverse systems by diversifying the operating modes. This has led to the development of DRAM provided with a variety of operating modes.
For example, DRAM is recently designed to perform a high-speed access mode called "page mode". To understand this mode, it is important to understand that the greatest part of a DRAM cycle is occupied by the time from word line selection to sense amplifier operation and by the precharge time following these operations. Page mode is a reading mode that eliminates this time.
More specifically, when the row address is fixed, page mode allows the row address to remain fixed and specifies column addresses in order to serially and continuously access sequential portions of the sense amplifier by the number of bits specified in the column addresses.
By performing read operations using page mode, the cycle time, that is the time from the beginning of one access to the beginning of the next, can be reduced to about 1/3 that in normal mode, thereby enabling the performance of high-speed operations in DRAM.
Further, now DRAM designed to perform an EDO (Extended Data Out) page mode has been developed. This EDO page mode can achieve a data transfer rate even faster than the page mode described above. Conventional DRAM uses an output control method during a read cycle to place output data in a state of high impedance on the rising edge of a column address strobe (CAS) signal. Accordingly, when the CAS signal rises, in conventional DRAM, the effect is to disable the input and output data. In contrast, output data in the EDO page mode is still maintained even when the CAS signal is switched to High. Hence, the cycle time in EDO page mode can be further reduced over the fast page mode.